Development of Indium Bumping and Flip-Chip
Technology for Cadmium Zinc Telluride Detector Arrays
NASA has expressed strong interest in flip-chip bonding
large, cadmium zinc telluride (CdZnTe), 64 x 64 arrays (4096 flip-chip bump
contacts) to silicon ASIC processor chips for use in IR detector focal planes
in NASA Hard X-ray astrophysics applications. Indium is very desirable as
a bump metallurgy for this application since it has excellent fatigue characteristics
at cryogenic temperatures. To date, these large detectors have not been successfully
bonded, primarily due to the small height of the as-fabricated indium bumps
(10-15 microns). Small amounts of camber in either the CdZnTe array detector
or the silicon processor chip can cause the bumps on both devices to pull
away after bonding, resulting in open circuits. To improve the flip-chip bonding
yield, the height of the indium bumps needs to be significantly increased.
The small size of the contact pads makes fabricating tall bumps extremely
challenging.
This project will enable APL to develop an indium bump
bonding process for fabrication of fine pitch, large area detector arrays for
gamma ray and cosmic ray imaging detectors.
Advanced Interconnection Technology
with Flip Chips and Chip Scale Packages Using Solder and Anisotropic Conductive
Adhesive in Electronic Packaging Miniaturization
Flip chips (FCs) and Chip Scale Packages (CSPs) can support higher density interconnect
without compromising component size and weight. While FCs demonstrate better
thermal performance and faster speed due to elimination of one entire level
of packaging, CSPs are compatible with the traditional surface-mount technology,
easier to handle and better in testability. Many companies provide CSPs as the
miniaturized version of the packaged parts for integrated circuit design. Anisotropic
Conductive Adhesives (ACAs), on the other hand, is an interconnection material
maintains electrical conductivity only in the out-of-plan direction.
The combination of ACAs with fine pitch FCs and CSPs can
lead to ultra-high density circuit design and further miniaturization of space
electronics. Furthermore, ACAs in FCs serve as both the electrical interconnections
and mechanical stress relievers, thus eliminating completely the procedures
of underfilling and flux cleaning.
The objective of this study is to investigate the feasibility
and reliability of using traditional solder material, as well as
ACA as interconnections in FCs and CSPs for space electronics.
Ultra High Density Substrate
Design with Small Feature Sizes, Embedded Passive Components
Substrate design plays an important role in the miniaturization of electronics
next to electronic devices. High density substrate can accommodate more parts
for a given area, thus reduces the weight and volume of the final system. In
this project, the ultra high density board design will employ high
density interconnect such as very small feature sizes in line width and spacing,
together with blind and buried vias with high aspect ratio. We will investigate
commercial technologies with additive processes together with etching processes
in producing low cost substrates.
In this study, we will investigate
- the reliability assessment of low cost high density substrates;
- methods of implementing this high density substrate design
in flight hardware; and
- methods of embedding passive components inside the substrates.
Minitature GPS Receiver
The use of autonomous GPS navigation systems on earth science missions will
enable lower cost programs by greatly increasing the level of spacecraft autonomy,
thereby reducing mission operations costs. It has also been demonstrated that
the use of spaceborne GPS increases the scientific return of earth science missions
by providing on-orbit real-time and ground-based orbit determination. Furthermore,
designs have been developed at APL, funded by GSFC, for integrated GPS positioning,
crosslink communications, and relative navigation systems. With the TIMED mission
design, GPS systems have been shown to be critical for event-based commanding
mission operations. With the decision by the GPS JPO to embark on a GPS modernization
program which will provide two additional civilian frequencies, it is clear
that the importance of spaceborne GPS applications will continue to grow.
Existing spaceborne GPS receivers and navigation systems
are much larger and significantly more expensive than modern spacecraft designers
require. With the evolving trend toward low cost satellites and missions, and
formation flying and distributed spacecraft mission architectures, lower cost
and more highly integrated and lower power GPS navigation systems are required.
Radiation tolerance and system-level autonomy are also critical requirements
for future systems. Space qualified, miniature, and highly integrated GPS navigation
and crosslink communications systems will represent a critical enabling technology
for a host of individual and distributed spacecraft earth science missions.
Command and Data Handling
in Your Palm(CDH- IYP)
This purpose of this initiative is to fabricate and test a module that demonstrates
a complex application of the JHU/APL COB process. The module chosen is the RTX2010
processor and interface module that was designed and breadboarded under a previous
NASA/GSFC C&DH-IYP grant. The module consists of a 4” x 4” aluminum
frame that encloses a 10-layer polyimide multi-layer PC. The module is designed
to stack with and communicate with similar modules using the IEEE-1394 serial
bus. The board design is a good candidate for demonstrating the APL Chip-On-Board
(COB) process because it includes devices in a variety of package types. The
board design includes bare die, Actel FPGA die packaged on snapstrate adapters,
a laser programmed ASIC die, packaged semiconductors, an infrared transceiver,
miniature nanonics I/O connectors and a fuzz button inter-board connector. As
a further challenge, the pad density on the laser programmed ASIC requires the
pads on the board to be staggered on two different board layers. Parts for the
module are already in stock. The IEEE-1394 chip already in stock will be used
if debugging indicates that the chip is sufficiently functional, otherwise the
IEEE-1394 interface will be left off. In addition to fabricating the COB version
of the board, test software must be completed that will fully exercise the hardware.
A tester and thermal-vacuum cables for the board already exist.
Once the COB version of the board is fabricated and tested,
it will be environmentally tested to demonstrate the ruggedness of the COB process.
A three-axis vibration test and thermal vacuum tests will be performed. When
testing is complete, a report/paper will be developed documenting the results.
Miniaturized High Voltage
Circuit Design
The primary objective of this study is to develop the advanced techniques necessary
to design miniature high voltage circuits that can be qualified for safe and
reliable space flight operations. The study will investigate the behavior of
high voltage circuit designs with respect to changes in dielectric and conductive
materials, conductor lengths and shapes, and topologies of ground planes. Once
these techniques are demonstrated, the second objective of this project is to
implement and evaluate an advanced miniaturized high voltage section in the
power supply design.
Integrated Power Source
The Integrated Power Source (IPS) has advantages over other spacecraft power
systems in that it comprises an integrated assembly (solar cell array, housing,
battery, and charge management system) rather than a set of separate add-on
components and therefore offers improved packaging efficiency. In the IPS design,
solar cells will be directly laminated onto a layer of battery, which in turn
is laminated onto the support electronics substrate. The IPS can accommodate
several state-of-the-art secondary battery technologies including lithium ion,
lithium ion polymer, and solid state polymer as the main energy storage unit.
The IPS electronics is a microprocessor-based power management
system that executes charge control software that accommodates several battery
chemistries and autonomously monitors and corrects conditions that can result
in battery failure. The charge control processor performs individual cell charge
control, and maintains cell matrix charge state equality as required by the
lithium-ion polymer and all polymer battery chemistries. The IPS electronics
substrate assembly will be implemented with advanced Chip-on-Board (COB) technology.
The development of the IPS concept is an enabling technology
for new microsat architectures in which dedicated power sources provide regulated
power for spacecraft instruments and/or subsystems. This study will specifically
investigate the feasibility of implementing the IPS for microsat applications.
The development of a microsat system configuration to best utilize the new IPS
technology will be part of this development. A conceptual system design, including
preliminary system level requirements, will be developed in conjunction with
the new power system architecture.
Techniques for controlling temperature distribution through
the IPS structure will be examined. Through careful material selection and laminate
structure design, intermediate layers within the panel will be maintained at
temperatures that best suit the battery and power control electronics.
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